Integrated circuits (ICs) have become the backbone of modern consumer electronics. The increased demand for functionality of consumer electronics has forced the complexity of IC's to skyrocket. In a number of applications, ICs must be highly functional, low cost and have low power consumption. These demands create increased complexity on the design, verification, and manufacture of ICs.
A typical IC design may involve the creation of electronic components, such as transistors and resistors, and the interconnections of these components onto a substrate, such as silicon. Functional verification of a digital design involves the verification that the design conforms to the specification. Functional verification may involve the validation that a design meets the desired functionality. Part of the process of verification includes the creation of Register Transfer Level (RTL) digital designs that describe in detail the functionality of the device or block at every cycle of the clock. Creation and verification RTL design may be one of the more difficult portions of the design process. In many instances, this verification is a very difficult and time intensive task. Simulation tools are typically used to assist in verification. In most designs, simulation-based functional verification is performed on multiple machines in parallel. During the verification process, “coverage” data is produced that indicates which portions of the functionality and/or code have been tested.
Many contemporary verification flows in industry have adopted a combination of formal property checking and constrained random testing. At their core, both approaches require efficient constraint solving, but formal verification typically seeks out a single solution. In constrained random testing the generation of the stimulus set requires repeated generation of solutions with a good distribution (e.g., uniform) over the solution space. A number of approaches to constrained problem solutions and to stimulus generation for constrained random testing have been used in the art. The efficiencies of these approaches typically fail in either their ability to provide good uniform distribution of stimulus over the solution set, or in their run-time and memory efficiency. Further, some approached perform well for small problems but their performance degrades substantially with the size of the problem.
Therefore there exists a need for a system, and methods for improved stimulus generation for verification of digital design descriptions. One that can produce an appropriate distribution of stimulus in an efficient manner and that scales well to large problems.